This invention relates to a nonvolatile semiconductor memory device and its manufacturing method.
There is known an electrically rewritable, nonvolatile semiconductor memory (Flash) using memory cells of a stacked-gate structure stacking floating gates and control gates. This kind of Flash uses a tunneling insulation film as a first gate insulating film between floating gates and a semiconductor substrate and typically uses, as the second gate insulating film between floating gates and control gates, an ONO film which is a multi-layered film of a silicon oxide film (O) on a silicon nitride film (N) on a silicon oxide film (O).
Each memory cell is formed in an element-forming region partitioned by an element isolation/insulation film. In general, a floating gate electrode film is divided in the direction of control gate line (word line) by making a slit on the element isolation/insulation film. In the step of making the slit, division of floating gates in the bite-line direction is not yet done. Then a control gate electrode film is stacked via an ONO film on all surfaces of the substrate including the top of the slit-processed floating gate electrode film, and by sequentially etching the control gate electrode film, ONO film, and floating gate electrode film, control gates and floating gates are then isolated in the bit-line direction. After that, source and drain diffusion layers are formed in self-alignment with the control gates.
FIG. 1 is a schematic view of a conventional method for manufacturing a non volatile semiconductor memory device structure, wherein FIGS. 2A and 2B are schematic sectional views of cutting lines taking along III-III′ and IV-IV′ of FIG. 1. FIG. 2A is a sectional view taken along line III-III′ of FIG. 1, and FIG. 2B is a sectional view taken along line IV-IV′. FIGS. 2A and 2B, reference numeral 101 denotes a P-type semiconductor substrate, reference numeral 107 denotes an N-well, reference numeral 201 denotes a P-well, reference numeral 301 denotes a field oxide film for dividing the semiconductor substrate into an active region and a non-active region, reference numeral 350 denotes a gate insulating film, reference numeral 370 denotes a source/drain region, reference numeral 401 denotes a floating gate, reference numeral 450 denotes an inter-dielectric layer, reference numeral 501 denotes a control gate, and reference numeral 600 denotes a first insulating film.
Refer to FIGS. 2A and 2B, on the P-type (or alternatively, N-type) semiconductor substrate 101, an ion implantation is performed at various steps, the field oxide 301, the gate insulation 350, the floating gate 401, the inter-dielectric layer 450 and the control gate 501 are sequentially deposited. On each side of the gates, N-type (or alternatively, P-type) source/drain regions 370 are formed. The first insulating film 600 is formed on the source/drain regions 370, on the sidewalls of both the floating gate 401, the control gate 501 and on top of the control gate 501 as shown in FIG. 2B.
The first insulating film 600 acts as a dielectric layer to electrically isolate the source/drain 370, the floating gate 401 and the control gate 501 from the PA-plate 700. The first insulating film 600 has a predetermined permittivity and consists of, for example, an oxide film, a nitride film, an oxy-nitride film, an oxide-nitride-oxide laminate (ONO) films or a combination of such films such as a nitride film and an oxide film.
FIGS. 3A-5B are sectional views for illustrating the conventional manufacturing method of a nonvolatile memory device. FIGS. 3A, 4A and 5A are sectional views taken along the cutting line III-III′ of FIG. 1, and FIGS. 3B, 4B and 5B are sectional views taken along the cutting line IV-IV′ of FIG. 1.
FIGS. 3A and 3B show a step of forming a field oxide film 301 and a gate oxide film 350 on a P-type portion 201 of a semiconductor substrate 101. Alternatively, the structures are formed on an N-type portion of a semiconductor substrate without departing from the scope of this invention.
Referring to FIGS. 3A and 3B, a second conductivity type well 107 is formed in a first conductivity type semiconductor substrate 101, and a first conductivity type well 201 is formed in the second conductivity type well 107. A field oxide film 301 is formed on a surface of the substrate where the first and second conductivity type wells are formed for a purpose of electrically isolating the active devices, and a gate oxide film 350 is formed on the resultant structure. The gate oxide film 350 can be formed before forming the field oxide film 301.
FIGS. 3A and 3B show N-type impurities implanted into a predetermined region of a P-type semiconductor substrate 101 by using the photolithography and the ion-implantation methods. The ion-implanted region is diffused to a desired depth by heat treating at a high temperature in order to form the N-well 107. The P-well 201 is formed by using the same method on a predetermined region of the N-well 107. The isolation film 301 is formed by an isolation method, for example, shallow trench isolation (STI), and a thin thermal oxide film is grown on the entire surface of the formed isolation film to form a gate oxide film 350 on the isolation film.
FIGS. 4A and 4B show the steps of forming a floating gate 401, an inter-dielectric layer 450 and a control gate 501. A floating gate 401 is formed on the gate oxide film 350; an inter-dielectric layer 450 having a predetermined thickness is formed on the isolation film 301, the gate oxide film 350 and the floating gate 401; and a control gate 501 is formed on the inter-dielectric layer 450.
FIGS. 4A and 4B, a conductive material is used for forming a gate electrode, wherein polysilicon is used and doped with impurities, and the polysilicon is then deposited on the gate oxide film 350 and patterned by a chemical mechanical polish(CMP) process for forming a floating gate so that, the formation of the floating gate 401 can be achieved. An insulation film is deposited on the floating gate 401, such as a sequentially deposited oxide film, nitride film and oxide film (ONO film) to form an inter-dielectric layer 450. The inter-dielectric layer 450 insulates the floating gate 401 from the control gate 501, and acts as a dielectric layer over the floating gate 401.
The select transistors operate as typical transistors rather than as floating gate storage devices. Therefore, in the areas where select transistors are to be formed part of, the control gate 501 and the inter-dielectric 450 are patterned to create contact holes so that a contact between the floating gate 401 and the select transistor is created.
The conventional method of forming a nonvolatile memory device, additional processes are required to form the floating fate 401 due to the different structures in element-forming regions between the floating gate 401 and the selected gate areas.